Analysis and Performance of a Scalable Gigabit Active Router

Modern networks require the flexibility to support new protocols and network services without changes in the underlying hardware. Routers with general-purpose processors can perform data path packet processing using software that is dynamically distributed. However, custom processing of packets at link speeds on a high performance router requires immense computational power. Single workstation processors are unsuitable for this purpose because they are designed for few large tasks. Network processors need to handle packets from thousands of independent flows and switch between many small tasks at a much finer granularity. The router architecture proposed here uses multiple network processors with cache and memory on a single application specific integrated circuit (ASIC) to overcome the limitations of traditional workstation processors. Each router port can be equipped with multiple such processing units to scale to its computational needs. Application benchmarks and simulations are used to analyze design tradeoffs and develop a fair scheduling scheme for this multiprocessor environment.